Semiconductor integrated circuit device and manufacturing method thereof

ABSTRACT

A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor integratedcircuit device and a manufacturing method of the same. Moreparticularly, the present invention relates to a technique effectivelyapplicable to a semiconductor integrated circuit device, in which a DRAM(Dynamic Random Access Memory) and a logic circuit are mounted together,and a manufacturing method of the same.

BACKGROUND OF THE INVENTION

[0002] The DRAM has a MISFET (Metal Insulator Semiconductor Field EffectTransistor) for data transfer and a capacitor for data storage connectedin series to this MISFET. This capacitor for data storage is formed by,for example, sequentially depositing silicon to be a lower electrode,tantalum oxide to be a capacitor insulating. film, and a refractorymetal film to be an upper electrode.

[0003] Also, in this capacitor for data storage, the scaling. down ofthe device and the increase of the capacitance thereof are achieved byforming a deep hole through the insulating film and then forming a lowerelectrode and a capacitor insulating film on the side wall and thebottom surface of the hole.

[0004] For further increase of the capacitance, a technique is employedin which projections made of silicon grains are provided on a surface ofthe silicon to be a lower electrode to create surface irregularities,and thereby increasing the surface area. The projections made of silicongrains are called HSG (Hemispherical Grained) silicon or rugged silicon.

[0005] A technique capable of effectively forming the HSG polysilicon isdisclosed in, for example, Japanese Patent Application Laid-OpenPublication No. 2000-22110. This technique is briefly described asfollows: Moisture contained in an interlayer insulating film is desorbedand the desorbed moisture reacts to the polysilicon film below theinterlayer insulating film during the high temperature heat treatmentfor forming the HSG polysilicon film. As a result, an SiO₂ film isformed on the surface of the polysilicon film. For its prevention, aheat treatment at a temperature higher than the temperature at which themoisture is desorbed is performed immediately before the above-describedhigh temperature heat treatment.

SUMMARY OF THE INVENTION

[0006] Inventors of the present invention have been engaged in researchand development of the DRAM and the like, and have been attempting toincrease the capacitance by means of the introduction of the ruggedpolysilicon.

[0007] However, since the growth of the rugged polysilicon is hindereddue to the effect of the moisture in the insulating film on which therugged polysilicon is formed, it is difficult to obtain the sufficientsurface area of the rugged polysilicon. Thus, such a method is underconsideration that a high temperature heat treatment is performed toremove the moisture in the insulating film, and then, to have the ruggedpolysilicon grown. In this case, however, the properties of the MISFETin the under layer are deteriorated due to the high temperature heattreatment.

[0008] Especially, in the so-called system LSI (Large Scale IntegratedCircuit) in which the DRAM and the logic LSI are formed on the samesemiconductor substrate, the logic circuit is formed by appropriatelycombining an n channel MISFET and a p channel MISFET, and the propertiesof these MISFETs are deteriorated due to the high temperature heattreatment.

[0009] For example, in these MISFETs, a so-called dual gate structure isemployed, in other words, an n type gate electrode is used as the gateelectrode of the n type MISFET and a p type gate electrode is used asthe gate electrode of the p type MISFET. This is because if an n typegate electrode is used as the gate electrode of the p type MISFET, thechannel thereof is formed at the position apart from the substratesurface (embedded channel), and the control of the potential applied tothe gate electrode becomes difficult.

[0010] However, boron (B) implanted to make the p type gate electrode isprone to diffuse (leak) by the heat treatment. If the boron is diffusedinto the semiconductor substrate through a gate insulating film, theconcentration profile of the semiconductor substrate is changed,resulting in the deterioration of its properties (e.g., variation of thethreshold voltage).

[0011] In addition to the concentration profile of the semiconductorsubstrate, the heat treatment causes an adverse effect on variousproperties of the MISFET such as the concentration profile of the sourceand drain regions of the MISFET.

[0012] It is an object of the present invention to reduce the load dueto the heat treatment to a semiconductor integrated circuit devicehaving a DRAM memory cell.

[0013] It is another object of the present invention to improve theproperties of a DRAM memory cell.

[0014] It is another object of the present invention to improve theproperties of a semiconductor integrated circuit device having a DRAMand a logic circuit constituted of an n channel MISFET and a p channelMISFET.

[0015] The above and other objects and novel characteristic of thepresent invention will be apparent from the descriptions and theaccompanying drawings of this specification.

[0016] The typical ones of the inventions disclosed in this applicationwill be briefly described as follows.

[0017] 1. In an aspect of the manufacturing method of a semiconductorintegrated circuit device according to the present invention, aninsulating film is formed above a MISFET of a memory cell, which isformed of the MISFET and a capacitor formed on a main surface of asemiconductor substrate, by the plasma CVD method at a temperature of450° C. to 700° C.; a trench is formed by etching the insulating film;and a silicon film is deposited on the insulating film and in thetrench, and then, the silicon film on the insulating film is removed toform a lower electrode of the capacitor on the inner wall of the trench.

[0018] 2. In another aspect of the manufacturing method of asemiconductor integrated circuit device according to the presentinvention, a first insulating film is deposited above a MISFET of amemory cell, which is formed of the MISFET and a capacitor formed on amain surface of a semiconductor substrate, at a predeterminedtemperature; a second insulating film is deposited on the firstinsulating film at a temperature higher than the predeterminedtemperature; a trench is formed by etching the first and secondinsulating films; and a silicon film is deposited on the secondinsulating film and in the trench, and then, the silicon film on thesecond insulating film is removed to form a lower electrode of thecapacitor on the inner wall of the trench.

[0019] 3. In another aspect of the manufacturing method of asemiconductor integrated circuit device according to the presentinvention, a MISFET is formed on a main surface of a semiconductorsubstrate; and then, an insulating film containing an impurity is formedabove the MISFET by the plasma CVD method at a temperature of 450° C. to700° C.

[0020] 4. In another aspect of the manufacturing method of asemiconductor integrated circuit device according to the presentinvention, a MISFET is formed on a main surface of a semiconductorsubstrate; a first insulating film is deposited on the MISFET at apredetermined temperature and the surface of the first insulating filmis planarized; and then a second insulating film containing an impurityis formed on the first insulating film at a temperature higher than thepredetermined temperature.

[0021] 5. In an aspect of the semiconductor integrated circuit deviceaccording to the present invention, the semiconductor integrated circuitdevice is provided with a MISFET formed on a main surface of asemiconductor substrate; and a capacitor connected in series to theMISFET,

[0022] wherein the capacitor is provided with a lower electrode made ofa silicon film, which is formed at a concave portion in a laminationlayer of a first insulating film formed above the MISFET and a secondinsulating film formed on the first insulating film and having smallerimpurity content than the first insulating film; a capacitor insulatingfilm formed on the lower electrode; and an upper electrode formed of aconductive film formed on the capacitor insulating film.

[0023] 6. In another aspect of the semiconductor integrated circuitdevice according to the present invention, the semiconductor integratedcircuit device is provided with a MISFET formed on a main surface of asemiconductor substrate; and a capacitor connected in series to theMISFET,

[0024] wherein the capacitor is provided with a lower electrode made ofa silicon film, which is formed at a concave portion in a laminationlayer of a first insulating film formed above the MISFET and a secondinsulating film which is thinner than the first insulating film andformed on the first insulating film; a capacitor insulating film formedon the lower electrode; and an upper electrode formed of a conductivefilm formed on the capacitor insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a cross-sectional view showing the principal part of asubstrate illustrating a manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0026]FIG. 2 is a cross-sectional view showing the principal part of thesubstrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0027]FIG. 3 is a cross-sectional view showing the principal part of thesubstrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0028]FIG. 4 is a cross-sectional view showing the principal part of thesubstrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0029]FIG. 5 is a cross-sectional view showing the principal part of thesubstrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0030]FIG. 6 is a cross-sectional view showing the principal part of thesubstrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0031]FIG. 7 is a cross-sectional view showing the principal part of thesubstrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0032]FIG. 8 shows graphs for explaining the results obtained in theembodiment of the present invention;

[0033]FIG. 9 shows graphs for explaining the results obtained in theembodiment of the present invention;

[0034]FIG. 10 shows graphs for explaining the results obtained in theembodiment of the present invention;

[0035]FIG. 11 shows graphs for explaining the results obtained in theembodiment of the present invention;

[0036]FIG. 12 is a cross-sectional view showing the principal part ofthe substrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

[0037]FIG. 13 is a cross-sectional view showing the principal part of asubstrate illustrating a manufacturing method of a semiconductorintegrated circuit device according to the second embodiment of thepresent invention;

[0038]FIG. 14 is a cross-sectional view showing the principal part ofthe substrate illustrating the manufacturing method of a semiconductorintegrated circuit device according to the second embodiment of thepresent invention;

[0039]FIG. 15 is a cross-sectional view showing the principal part of asubstrate illustrating a manufacturing method of a semiconductorintegrated circuit device according to the third embodiment of thepresent invention; and

[0040]FIG. 16 is a cross-sectional view showing the principal part of asubstrate illustrating a manufacturing method of a semiconductorintegrated circuit device according to the fourth embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] Hereinafter, embodiments of the present invention will bedescribed based on the drawings. Note that components having the samefunction are denoted by the same reference symbol throughout thedrawings for describing the embodiments, and the repetitive descriptionthereof will be omitted.

First Embodiment

[0042] The manufacturing method of the DRAM in this embodiment will bedescribed with reference to FIGS. 1 to 12 along-with the process flow.Note that an area in which a DRAM memory cell is formed (memory cellforming area (MCFA)) is on the left side of each cross-sectional viewshowing the semiconductor substrate, and an area in which a logiccircuit or the like of the DRAM is formed (logic circuit forming area(LCFA)) is on the right side of the same.

[0043] In this memory cell forming area, a memory cell constituted of aMISFET Qs for data transfer and a capacitor C for data storage isformed, and in this logic circuit forming area, an n channel MISFET Qnand a p channel MISFET Qp constituting a logic circuit are formed.

[0044] First, as shown in FIG. 1, a semiconductor substrate 1(hereinafter, referred to as a substrate) is etched to form a trench.Thereafter, a silicon oxide film 7 is embedded into this trench to forma device isolation 2. Next, after p type impurities (e.g., boron (B))and n type impurities (e.g., phosphorus (P)) are ion-implanted into thesubstrate 1, the heat treatment is performed to diffuse theseimpurities, and thus, a P well 3 is formed on the substrate 1 in thememory cell forming area, and a P well 3 and an N well 4 are formed onthe substrate 1 in the logic circuit forming area.

[0045] Next, for adjustment of the threshold voltages of the MISFET Qsfor data transfer and the n channel MISFET Qn, impurities areion-implanted into the P wells 3 on which these MISFETs are formed.Also, for adjustment of the threshold voltage of the p channel MISFETQp, impurities are ion-implanted into the N well 4 on which theseMISFETs are formed.

[0046] Next, the surface of the substrate 1 (P well 3 and N well 4) iswet cleaned with using cleaning liquid containing hydrofluoric acid.Thereafter, a clean gate oxide film 8 is formed on each of the surfacesof the P well 3 and the N well 4 by means of thermal oxidation.

[0047] Next, a low-resistance polycrystalline silicon film (9 a) isdeposited to a thickness of about 100 nm on the gate oxide film 8 by theCVD (Chemical Vapor Deposition) method. Subsequently, phosphorous (P)ions are implanted into the low-resistance polycrystalline silicon filmson the P well 3 in the logic circuit forming area and the memory cellforming area, and thereby forming an n type low-resistancepolycrystalline silicon film. Next, boron ions are implanted into thelow-resistance polycrystalline silicon film on the N well 4 in the logiccircuit forming area, and thereby forming a p type low-resistancepolycrystalline silicon film. These n type and p type low-resistancepolycrystalline silicon films are denoted by 9 an and 9 pn,respectively.

[0048] Subsequently, a WN film 9 b having a thickness of about 5 nm anda W film 9 c having a thickness of about 80 nm are deposited on thelow-resistance polycrystalline silicon films (9 an and 9 ap) by thesputtering method, and further, a silicon nitride film 10 having athickness of about 220 nm is deposited thereon by the CVD method.

[0049] Next, dry etching is performed to the silicon nitride film 10,the W film 9 c, the WN film 9 b, and the polycrystalline silicon films(9 an and 9 ap) with using a photoresist film (not shown and referred toas a resist film, hereinafter) as a mask, thereby forming an n type gateelectrode 9 n and a p type gate electrode 9 p. More specifically, the ptype gate electrode 9 p is formed on the N well 4 in the memory cellforming area, and the n type gate electrode 9n is formed on each of theP well 3 in the memory cell forming area and the P well 3 in the logiccircuit forming area. This n type gate electrode 9 n is constituted ofthe n type polycrystalline silicon film 9 n, the WN film 9 b, and the Wfilm 9 c, and the p type gate electrode 9 p is constituted of the p typepolycrystalline silicon film 9ap, the WN film 9 b, and the W film 9 c.Also, a cap insulating film made of the silicon nitride film 10 isformed on each of these gate electrodes 9 n and 9 p. Note that the gateelectrode 9 n formed in the memory cell forming area functions as a wordline WL.

[0050] Next, phosphorus ions are implanted into the both sides below thegate electrodes 9 n in the memory cell forming area and the logiccircuit forming area, thereby forming n⁻ type semiconductor regions 11.Subsequently, boron fluoride (BF) ions are implanted into the both sidesbelow the gate electrode 9 p on the N well 4 in the logic circuitforming area, thereby forming p⁻ type semiconductor regions 12.

[0051] Next, as shown in FIG. 2, a silicon nitride film 13 is depositedto a thickness of about 50 nm on the resultant structure on thesubstrate 1 by the CVD method. Thereafter, the upper portion of thesubstrate 1 in the memory cell forming area is covered with a resistfilm (not shown), and anisotropic etching is performed to the siliconnitride film 13 in the logic circuit forming area, thereby forming asidewall spacer on the sidewall of each of the gate electrodes 9 n and 9p in the logic circuit forming area.

[0052] Next, arsenic (As) ions are implanted into the both sides belowthe gate electrodes 9 n on the P well 3 in the logic circuit formingarea, thereby forming n⁺ type semiconductor region 14 (source anddrain). Subsequently, boron fluoride (BF) ions are implanted into theboth sides below the gate electrode 9 p on the N well 4 in the logiccircuit forming area, thereby forming a p⁺ type semiconductor region 15(source and drain).

[0053] At the end of the steps described above, the n channel MISFET Qnand the p channel MISFET Qp, each of which is provided with a source anda drain (n⁻ type semiconductor region 11 and n⁺ type semiconductorregion 14, and p⁻ type semiconductor region 12 and p⁺ type semiconductorregion 15) having LDD (Lightly Doped Drain) structure, are formed in thelogic circuit forming area, and the MISFET Qs for data transferconstituted of the n channel MISFET is formed in the memory cell formingarea.

[0054] As described above, if the n type gate electrode 9 n is used asthe gate electrode of the n channel MISFET Qn in the logic circuitforming area and the p type gate electrode 9 p is used as the gateelectrode of the p channel MISFET Qp (so-called a dual gate structure),the channel is formed on the surface of the substrate, and thus, thesubthreshold characteristics and the short channel effect can beimproved.

[0055] Next, after forming a silicon oxide film 16 over the gateelectrodes 9 n and 9 p, the silicon oxide film 16 on the n⁻ typesemiconductor region 11 in the memory cell forming area is dry-etchedwith using a resist film (not shown) as a mask to expose the surface ofthe silicon nitride film 13. Thereafter, the exposed silicon nitridefilm 13 is dry-etched to form contact holes 18 and 19 on the n⁻ typesemiconductor regions 11.

[0056] Next, arsenic (As) ions are implanted through the contact holes18 and 19 to form an n⁺ type semiconductor region 17. Subsequently, aplug 20 is formed in each of the contact holes 18 and 19. The plug 20 isformed in such a manner as follows. That is, a low-resistancepolycrystalline silicon film in which n type impurities such asphosphorus (P) are doped is deposited on the silicon oxide film 16 andin the contact holes 18 and 19 by the CVD method, and subsequently, thepolycrystalline silicon film is polished by the CMP (Chemical MechanicalPolishing) method so as to leave the polycrystalline silicon film onlyin the contact holes 18 and 19.

[0057] Next, as shown in FIG. 3, after depositing a silicon oxide film21 to a thickness of about 20 nm on the silicon oxide film 16 by the CVDmethod, the silicon oxide film 21 and the silicon oxide film 16 below itin the logic circuit forming area are dry-etched with using a resistfilm (not shown) as a mask. By so doing, contact holes 22 are formed onthe n⁺ type semiconductor region 14 of the n channel MISFET Qn, andcontact holes 23 are formed on the p⁺ type semiconductor region 15 ofthe p channel MISFET Qp. Simultaneous with this, a through hole 25 isalso formed on the plug 20 formed inside the contact hole 18 in thememory cell forming area.

[0058] Subsequently, a cobalt (Co) film is deposited on the siliconoxide film 16 and in the contact holes 22 and 23 in the logic circuitforming area by the sputtering method, and a cobalt silicide (CoSi)layer S is formed by the silicidation reaction at a contact pointbetween the Co film and the n⁺ type semiconductor region 14 and the p⁺type semiconductor region 15 in the logic circuit forming area. Andthen, the unreacted Co film is removed.

[0059] The silicide layer S is formed on the source and drain regions(n⁺ semiconductor region 14 and p⁺ semiconductor region 15) of theMISFET in the logic circuit forming area as described above, which makesit possible to reduce the contact esistance between a plug 27 describedlater and the source and drain regions. Therefore, it becomes possibleto achieve higher operation speed of the logic circuit constituted ofthe MISFETs.

[0060] Next, the plugs 27 are formed in the contact holes 22 and 23 andin the through hole 25. This plug 27 is formed in such a manner asfollows. That is, after a thin TiN film is deposited on the siliconoxide film 21, in the contact holes 22 and 23, and in the through hole25 by the CVD method, a W film is deposited thereon, and then, the Wfilm and the TiN film on the silicon oxide film 21 are polished by theCMP method to leave these films only in the contact holes 22 and 23 andin the through hole 25.

[0061] Next, a bit line BL is formed on the silicon oxide film 21 in thememory cell area, and first wirings 30 to 32 are formed on the siliconoxide film 21 in the logic circuit forming area. The bit line BL and thefirst wirings 30 to 32 are formed in such a manner as follows. That is,after depositing a W film on the silicon oxide film 21 by the sputteringmethod, the W film is dry-etched with using a resist film as a mask.

[0062] Next, as shown in FIG. 4, a silicon oxide film 34 is formed onthe bit line BL and the first wirings 30 to 32.

[0063] Next, the silicon oxide film 34 and the silicon oxide film 21below it in the memory cell forming area are dry-etched to form athrough hole 38 on the plug 20 in the contact hole 19.

[0064] Next, a plug 39 is formed in the through hole 38. The plug 39 isformed in such a manner as follows. That is, after depositing alow-resistance polycrystalline silicon film which is doped with n typeimpurities (e.g., phosphorus) on the silicon oxide film 34 and in thethrough hole 38, the polycrystalline silicon film is polished by the CMPmethod so as to leave the polycrystalline silicon film only in thethrough hole 38.

[0065] Next, as shown in FIG. 5, a silicon nitride film 40 is depositedto a thickness of about 100 nm on the silicon oxide film 34 and the plug39 by the CVD method, and subsequently, a silicon oxide film 41 isdeposited to a thickness of about 1.4 μm on the silicon nitride film 40by the CVD method.

[0066] The silicon oxide film 41 is formed by the high-density plasmaCVD method with using monosilane (SiH₄) and oxygen as materials. Thedeposition temperature (substrate temperature) at this time is set in arange of 450° C. to 700° C.

[0067] In this embodiment, the silicon oxide film 41 having a capacitorC formed on the surface thereof is formed by the plasma CVD method at ahigh temperature of 450° C. to 700° C. as described above. Therefore, itis possible to form the silicon oxide film 41 having low moisture andimpurity contents. The impurity mentioned here is a by-product materialcreated during the film formation (gas-phase reaction).

[0068] In addition to monosilane, for example,, tetraethoxysilane (TEOS)can also be used as a material thereof. If tetraethoxysilane is used,carbon and carbon compound are created as by-product materials. Notethat the high-density plasma CVD method is employed in this embodiment,however, the regular plasma CVD method can also be used if the processtemperature is set in a range of 450° C. to 700° C.

[0069] The high-density plasma CVD method is the CVD performed in alow-pressure atmosphere having a high electron density. Morespecifically, the regular plasma CVD is performed at a pressure of 1 to10 Torr and an electron density of 1×10⁹ to 1×10¹⁰. On the other hand,the high-density plasma CVD is performed at a pressure of 0.001 to 0.01Torr (1 Torr=1.33322×10² Pa) and an electron density of 1×10¹² or more.Also, in the high-density plasma CVD method, the number of ions strikingthe substrate can be adjusted by controlling the current applied to thesubstrate, and thus, it is possible to control the substrate temperatureeasily.

[0070] Next, as shown in FIG. 6, the silicon oxide film 41 in the memorycell forming area is dry-etched with using a resist film (not shown) asa mask, and subsequently, the silicon nitride film 40 below the siliconoxide film 41 is dry-etched to form a trench 42 on each of the plugs 39.

[0071] Next, after depositing an amorphous silicon film 43 a which isdoped with n type impurities (phosphorus) to a thickness of about 50 nmon the silicon oxide film 41 and in the trenches 42, a resist film R isembedded to the trenches 42, and then, the amorphous silicon film 43 aon the silicon oxide film 41 is etched back, thereby leaving theamorphous silicon film 43 a on the inner wall of the trench 42.

[0072] Next, after removing the resist film R, the surface of theamorphous silicon film 43 a left in the trench 42 is wet cleaned withusing cleansing liquid containing hydrofluoric acid. Thereafter, asshown in FIG. 7, monosilane (SiH₄) is supplied to the surface of theamorphous silicon film 43 a in the low-pressure atmosphere.Subsequently, a heat treatment is performed to the substrate 1 at atemperature of about 600° C. to polycrystallize the amorphous siliconfilm 43 a, and thereby silicon grains 43 b are grown on the surface ofthe amorphous silicon film 43 a. Consequently, a polycrystalline siliconfilm 43 (43 a and 43 b) having irregularities on its surface is formedon the inner wall of the trench 42. The polycrystalline silicon film 43is used as a lower electrode of the capacitor C.

[0073] As described above, the silicon oxide film 41 is formed by theplasma CVD method at a high temperature of 450° C. to 700° C., andthereby, the silicon oxide film 41 having low moisture and impuritycontents is formed in this embodiment. Therefore, it is possible toreduce the amount of degassing from the silicon oxide film 41 when thesilicon grains are grown. As a result, since such gas does not hinderthe growth of the silicon grains and the supply of monosilane serving asa material of the silicon grains, it is possible to obtain sufficientsurface area of the polycrystalline silicon film 43.

[0074] More specifically, if the silicon oxide film 41 is fformed by theCVD method at a temperature of 400° C. or less, the degassing from thesilicon oxide film 41 hinders the growth of the silicon grains and thesupply of monosilane serving as a material of the silicon grains whenthe silicon grains are grown. Therefore, the surface area of thepolycrystalline silicon film 43 can not be obtained sufficiently.

[0075] In addition, it would be possible to remove the moisture andimpurities contained in the silicon oxide film 41 by performing a heattreatment after forming the silicon oxide film 41 and before forming theamorphous silicon film 43 a in order to reduce the degassing from thesilicon oxide film 41. However, in such a case where the silicon oxidefilm has already been formed thickly, the heat treatment must beperformed at a considerably high temperature and for a long time (e.g.,750° C. and two minutes).

[0076] If the heat treatment at high temperature and for a long timelike this is performed, the properties of the MISFETs Qs, Qn, and Qp aredeteriorated. More specifically, the concentration profiles of thesemiconductor regions constituting the source and drain of these MISFETsare changed, and as a result, it becomes impossible to maintain thedesired properties.

[0077] Also, in the case where the MISFET of dual gate structure isformed in the logic circuit forming area, the impurities in the gateelectrode may be diffused into the substrate through the gate insulatingfilm. Especially, boron (B) implanted into the p type gate electrode isprone to be diffuse (leak), and the properties thereof are deterioratedeasily.

[0078] Also, in such a case where a resistor device constituted of apolycrystalline silicon film and whose resistance value is controlled bythe impurity concentration in the film is formed in addition to theMISFETs, the diffusion of the impurities in the film causes theresistance value to change.

[0079] Also, since such leakage of the impurities occurs irregularly ineach device, it is quite difficult to implant impurities inconsideration of the leakage amount in advance.

[0080] To the contrary, since the silicon oxide film 41 is formed by theplasma CVD method at a high temperature of 450° C. to 700° C. in thisembodiment, the moisture and impurities can be removed during the filmformation, and also, the heat treatment step to remove the moisture orthe like after forming the silicon oxide film 41 can be omitted. Inother words, it becomes possible to reduce the amount of time requiredfor the heat treatment and to lower the temperature of the heattreatment.

[0081] Thus, since the heat load can be reduced, it is possible toprevent the deterioration of the properties of the MISFET, particularly,to reduce the leakage amount of boron.

[0082] Also, the reduction of the heat load makes it possible to preventthe wiring such as the bit line BL and first wirings 30 to 32 frompeeling and breaking.

[0083] Note that, as described above, since the silicon grains 43 b aregrown at a temperature of 600° C. in this embodiment, if the siliconoxide film 41 is formed at a temperature of 600° C. or more, the furtherreduction of the degassing amount during the growth of the silicongrains can be achieved.

[0084]FIG. 8 shows the moisture desorption properties of the siliconoxide films formed under various conditions below based on the TDS(Thermal desorption spectroscopy) analysis. That is, (a): the plasma CVDmethod is used, the temperature is set at 400° C., and tetraethoxysilaneis used as a material thereof, (b): the plasma CVD method in which twoplasmas of high and low frequencies are used, the temperature is set at400° C., and tetraethoxysilane is used as a material thereof, (c): theplasma CVD method is used, the temperature is set at 400° C., and gascontaining tetraethoxysilane and phosphorus is used as a materialthereof, and (d): the high-density plasma CVD method is used, thetemperature is set at 600° C., and monosilane is used as a materialthereof. The vertical axis in FIG. 8 represents the relative ionic (H₂O)strength per 1 cm², and when the amount of desorbed moisture is large,the value is also large. Also, the horizontal axis represents thetemperature. In the graph (a), the amount of the desorbed moisturestarts to increase at around the temperature over 600° C. and reachesits peak at around the temperature of 700° C. On the other hand, in thegraph (d), the amount of the desorbed moisture starts to increase ataround the temperature over 700° C. and reaches its peak at around thetemperature of 800° C. However, the amount in this case is considerablysmaller in comparison to the case of the graph (a). Note that as shownin the graph (b), in the case where the silicon oxide film is formed byusing the two plasmas of high and low frequencies, the moisturedesorption is improved in comparison to the case of the graph (a). Also,as shown in the graph (c), in the case where impurities (phosphorus) iscontained in the silicon oxide film, the moisture desorption is found ata lower temperature.

[0085]FIG. 9 shows the moisture desorption properties of each siliconoxide film shown in FIG. 8 after a heat treatment. The graph (al)represents the moisture desorption property in the case where thesilicon oxide film of the graph (a) is subjected to the heat treatmentat 750° C. for 2 minutes, the graph (a2) represents the moisturedesorption property in the case where the silicon oxide film of thegraph (a) is subjected to the heat treatment at 700° C. for 1 minute,the graph (b′) represents the moisture desorption property in the casewhere the silicon oxide film of the graph (b) is subjected to the heattreatment at 700° C. for 1 minute, the graph (c′) represents themoisture desorption property in the case where the silicon oxide film ofthe graph (c) is subjected to the heat treatment at 700° C. for 1minute, and, the graph (d′) represents the moisture desorption propertyin the case where the silicon oxide film of the graph (d) is subjectedto the heat treatment at 700° C. for 1 minute. As shown in the graphs(a1) and (a2), the amount of the desorbed moisture is reduced afterperforming the heat treatment to the film of the graph (a) (refer to thegraph (a) in FIG. 8). Also, as is apparent from the comparison of thegraphs (a1) and (a2), the amount of the desorbed moisture in the filmbecomes smaller if the film is subjected to the heat treatment at highertemperature and for a longer time. Also, in the graphs (b′) and (c′),the amount of the desorbed moisture is reduced after performing the heattreatment. On the other hand, as is apparent from the comparison of thegraphs (d′) and (d) in FIG. 8, the amount of the desorbed moisture inthe film formed according to the conditions shown in this embodiment isnot reduced even if the film is subjected to the subsequent heattreatment. This is considered because the moisture in the film issufficiently removed during the film formation.

[0086]FIG. 10 shows how much the silicon grains are grown when the heattreatment under different conditions is performed to each of the films,that is, the film of the graph (b) formed by the plasma CVD method usingtwo plasmas of high and low frequencies with using tetraethoxysilane asa material thereof, and the film of the graph (d) formed by thehigh-density plasma CVD method at a temperature of 600° C. with usingmonosilane as a material thereof. The occupancy (%) of the vertical axisrepresents how much the silicon grains (43 b) occupy the surface of thesilicon film (amorphous silicon film 43 a). This occupancy can beobtained by means of the image recognition of the silicon grains and theimage processing thereof.

[0087] As shown by the graph (b) in FIG. 10, in the case of the filmformed by the plasma CVD method using two plasmas of high and lowfrequencies with using tetraethoxysilane as a material thereof, thehigher the temperature of the heat treatment becomes, the higher theoccupancy becomes. Also, when the heat treatment is performed whilesetting the temperature constant, the longer the time of the subsequentheat treatment becomes, the higher the occupancy becomes.

[0088] On the other hand, in the case of the film formed by thehigh-density plasma CVD method at a temperature of 600° C. with usingmonosilane as a material thereof, the occupancy of about 63% can beobtained regardless of the temperature and the time of the heattreatment, and the occupancy of the same degree can be obtained even ifthe heat treatment is not performed. Therefore, in the case of the filmformed by the high-density plasma CVD method at a temperature of 600° C.with using monosilane as a material thereof, it is possible to obtainthe occupancy of 60% or more even if the subsequent heat treatment isnot performed.

[0089]FIG. 11 shows the capacitances in the case where the laterdescribed capacitor insulating film and upper electrode are formed oneach of the films shown in the graph (d) in FIG. 9. As shown in FIG. 11,in the case of the film formed by the high-density plasma CVD method ata temperature of 600° C. with using monosilane as a material thereof,the capacitance of 30fF or more can be obtained even if the subsequentheat treatment is not performed. The capacitance thus obtained isapproximately equal to that obtained after performing the heat treatmentat a temperature of 700° C. and for 1 minute. Therefore, in the case ofthe film formed by the high-density plasma CVD method at a temperatureof 600° C. with using monosilane as a material thereof, it is possibleto obtain the capacitance of 30 fF or more even if the subsequent heattreatment is not performed.

[0090] Next,. the steps of forming a capacitor insulating film and anupper electrode will be described. As shown in FIG. 12, after depositinga tantalum oxide (Ta₂O₅) film 44 to a thickness of about 10 nm on thesilicon oxide film 41 and in the trench 42 by the CVD method, the heattreatment is performed at a temperature of about 650° C. to 750° C. inan oxidizing atmosphere to crystallize the tantalum oxide film 44. Thetantalum oxide film 44 is used as the capacitor insulating film of thecapacitor C.

[0091] Next, a TiN film 45 is deposited to a thickness of about 100 nmon the tantalum oxide film 44 and in the trenches 42 by using the CVDmethod and the sputtering method together. Thereafter, the TiN film 45and the tantalum film 44 are dry-etched with using a resist film (notshown) as a mask. By so doing, a capacitor C constituted of an upperelectrode composed of the TiN film 45, a capacitor insulating filmcomposed of the tantalum oxide film 44, and a lower electrode composedof the polycrystalline silicon film 43 is formed. At the end of thesteps described above, a DRAM memory cell formed of the MISFET Qs fordata transfer and the capacitor C connected in series thereto iscompleted.

[0092] Next, a silicon oxide film 50 is deposited on the capacitor C bythe CVD method. Subsequently, the silicon oxide films 50 and 41, thesilicon nitride film 40, and the silicon oxide film 34, which are formedon the first wiring 30 in the logic circuit forming area, are subjectedto the dry etching to form a through hole 51. Thereafter, a plug 53 isformed in the through hole 51 in the same manner as that of the plug 27.

[0093] Next, second wirings 54 to 56 are formed on the silicon oxidefilm 50 and the plug 53. Subsequently, third wirings are formed on thesecond wirings 54 to 56 via a silicon oxide film, and then, a protectionfilm composed of a silicon oxide film and a silicon nitride film isdeposited on the third wirings. However, illustration of them isomitted. At the end of the steps described above, the DRAM according tothe embodiment has been almost completed.

[0094] Note that in this embodiment, a heat treatment is not performedafter, forming the silicon oxide film 41 and before forming theamorphous silicon film 43 a. However, it is also possible to perform aheat treatment, for, example, at a temperature of about 700° C. forabout 10 seconds.

Second Embodiment

[0095] In the first embodiment, the silicon oxide film 41 is formed bythe high-density plasma CVD method using monosilane (SiH₄) and oxygen asmaterials. However, the silicon oxide film having a two-layer structuremay be formed as described later.

[0096] The manufacturing method of a semiconductor integrated circuitdevice according to the second embodiment will be described withreference to FIGS. 13 and 14. Note that the steps until the plug 39 inthe silicon oxide film 34 is formed are the same as those in the firstembodiment described with reference to FIGS. 1 to 4. Therefore, thedescription thereof will be omitted.

[0097] As shown in FIG. 13, a silicon nitride film 40 is deposited to athickness of about 100 nm on the silicon oxide film 34 and the plug 39by the CVD method. Subsequently, a silicon oxide film 41 a is depositedto a thickness of about 0.5 to 2.0 μm on the silicon nitride film 40 bythe CVD method. Next, a silicon oxide film 41 b is deposited to athickness of 100 nm or more on the silicon oxide film 41 a.

[0098] This silicon oxide film 41 b is formed by the CVD method usingmonosilane (SiH₄) and oxygen as materials. Deposition temperature inthis case is set to about 450° C. to 700° C.

[0099] Next, as shown in FIG. 14, the silicon oxide films 41 a and 41 band the silicon nitride film 40 below them are dry-etched, and therebyforming trenches 42 above the plug 39.

[0100] Next, similar to the first embodiment, the lower electrodecomposed of the polycrystalline silicon film 43, the capacitorinsulating film composed of the tantalum oxide film 44, and the upperelectrode composed of the TiN film 45 are formed.

[0101] Further, the silicon oxide film 50, the plug 53, and the secondwirings 54 to 56 are formed in the same manner as that in the firstembodiment.

[0102] As described above, according to the second embodiment, thesilicon oxide film 41 b having the capacitor C formed on the surfacethereof is formed by the plasma CVD method at a high temperature of 450°C. to 700° C. Therefore, it is possible to form the silicon oxide film41 b with small moisture and impurity content. As a result, thedegassing from the silicon oxide films 41 a and 41 b, particularly, theamount of gas emitted from the upper surfaces thereof can be reduced asdescribed in the first embodiment. Therefore, the degassing does nothinder the growth of the silicon grains, and the sufficient surface areaof the polycrystalline silicon film 43 can be obtained.

[0103] Also, according to this embodiment, the heat treatment step forremoving the moisture or the like after forming the silicon oxide films41 a and 41 b can be omitted. In other words, it is possible to reducethe amount of time required for the heat treatment and to lower the heattreatment temperature. As a result, advantages as described in the firstembodiment can be obtained. More specifically, the deterioration ofproperties of the MISFETs can be prevented and, in particular, theleakage amount of boron can be reduced.

[0104] Further, according to this embodiment, only the silicon oxidefilm 41 b is formed by the CVD method at a high temperature of about450° C. to 700° C. Therefore, the peeling and breaking of the wiring(e.g., bit line BL and first wirings 30 to 32) due to the membranestress can be reduced. More specifically, if a detailed film with smallmoisture content is formed thinly, the membrane stress is increased andthe peeling and breaking of the wirings are prone to occur. However,according to this embodiment, it is possible to avoid such a problem.

[0105] In addition, when the high-density plasma CVD apparatus is used,since the apparatus itself is expensive, if the processing time usingthe apparatus is long, the product cost is increased. However, since thehigh-density plasma CVD apparatus is used only in the step of formingthe silicon oxide film 41 b in this embodiment, the product cost can bereduced.

Third Embodiment

[0106] In the above first and second embodiments, the present inventionis applied to the silicon oxide film on which the capacitor C is formed.However, it is also possible to apply the present invention to theinterlayer insulating film containing impurities such as phosphorus asdescribed below.

[0107]FIG. 15 is a cross-sectional view showing the principal part of asubstrate illustrating a manufacturing method of a semiconductorintegrated circuit device according to the third embodiment of thepresent invention.

[0108] The n channel MISFET Qn and the p channel MISFET Qp shown in FIG.15 can be made in the same manner as those of the MISFETs Qn and Qpdescribed in the first embodiment. Therefore, the description thereofwill be omitted.

[0109] As shown in FIG. 15, a silicon nitride film 60 is deposited onthe n channel MISFET Qn and the p channel MISFET Qp. This siliconnitride film 60 functions as an etching stopper when forming a contacthole on the source and drain regions (n⁺ type semiconductor region 14and p⁺ type semiconductor region 15). A plug is formed in the contacthole.

[0110] Subsequently, a silicon oxide film 61 to which impurities such asphosphorus (P) are added is deposited on the silicon nitride film 60.The impurities are contained in the silicon oxide film 61 as describedabove because the impurities function to capture the contaminants suchas heavy metal during the manufacturing process so as to protect thedevice such as the MISFET (so-called gettering).

[0111] The silicon oxide film 61 containing impurities is formed by thehigh-density plasma CVD method using the gas containing monosilane(SiH₄), oxygen, and phosphorus as a material. The deposition temperatureat this time is set to about 450° C. to 700° C.

[0112] As described above, in this embodiment, the silicon oxide film 61to which impurities such as phosphorus (P) are added is formed by theplasma CVD method at a high temperature of 450° C. to 700° C. Therefore,it is possible to form the silicon oxide film 61 with small moisturecontent and by-product content created during the film formation.

[0113] Therefore, the subsequent heat treatment step for removing themoisture and the by-product contained in the silicon oxide film 61 canbe omitted, or it is possible to reduce the amount of time required forthe heat treatment and to lower the heat treatment temperature. As aresult, the deterioration of properties of the MISFET can be prevented.

[0114] Especially, when impurities such as phosphorus (P) are containedin the silicon oxide film, the heat treatment after forming the filmbecomes important because of its high hygroscopicity. In the case wherethis heat treatment is performed after forming the film, the heattreatment at a high temperature and for a long time (e.g., 700 to 900°C. and 10 seconds to 30 minutes) is required. If the heat treatment at ahigh temperature and for a long time like this is performed, theconcentration profiles of the semiconductor regions constituting theMISFET are changed, and as a result, it becomes impossible to maintainthe desired properties as described in the first embodiment. Especially,the boron (B) implanted into the p type gate electrode 9 p is prone todiffuse and its property is lost easily.

[0115] Contrary to this, in this embodiment, the moisture and theby-product can be removed during the film formation. And thus, the heattreatment for removing the moisture or the like after forming thesilicon oxide film 61 can be omitted. In other words, it is possible toreduce the amount of time required for the heat treatment and to lowerthe heat treatment temperature.

[0116] Consequently, since it is possible to reduce the heat load, thedeterioration of properties of the MISFETs (Qn and Qp) can be prevented,especially, the leakage amount of boron in the p type gate electrode 9 pcan be reduced.

[0117] Thereafter, the plug and the like are formed in the silicon oxidefilm 61, and further, the first wiring is formed thereon. However, theillustration and the detailed description thereof will be omitted.

Fourth Embodiment

[0118] In the third embodiment, the silicon oxide film 61 is formed as asingle layer. However, the silicon oxide film having a two-layerstructure may be formed as described below.

[0119]FIG. 16 is a cross-sectional view showing the principal part of asubstrate illustrating a manufacturing method of a semiconductorintegrated circuit device according to the fourth embodiment of thepresent invention.

[0120] The n channel MISFET Qn and the p channel MISFET Qp shown in FIG.16 can be made in the same manner as those of the MISFETs Qn and Qpdescribed in the first embodiment. Therefore, the description thereofwill be omitted.

[0121] As shown in FIG. 16, a silicon oxide film 61 a is deposited abovethe n channel MISFET Qn and the p channel MISFET Qp by the CVD method.Note that if the high-density plasma CVD method is used here, theetching by the high-density plasma is performed simultaneously with thedeposition of the deposition material (silicon oxide in this case).Therefore, the silicon oxide can be properly embedded even in the finetrenches with a narrow width.

[0122] Next, the surface of the silicon oxide film 61 a is polished bythe CMP method to planarize the same.

[0123] Subsequently, a silicon oxide film 61 b to which impurities suchas phosphorus (P) are added is deposited on the silicon oxide film 61 a.The impurities are contained in the silicon oxide film 61 b for thepurpose of the gettering as described in the third embodiment.

[0124] The silicon oxide film 61 b containing impurities is formed bythe high-density plasma CVD method using the gas containing monosilane(SiH₄), oxygen, and phosphorus as a material. The deposition temperatureat this time is set to about 450° C. to 700° C.

[0125] As described above, the silicon oxide film 61 b containingimpurities on the MISFET is formed by the plasma CVD method at a hightemperature of 450° C. to 700° C. Therefore, it is possible to form thesilicon oxide film 61 b with small moisture and by-product content.

[0126] Therefore, similar to the third embodiment, the heat treatmentstep for removing the moisture and the by-product contained in thesilicon oxide film 61 b can be omitted, or it is possible to reduce theamount of time required for the heat treatment and to lower the heattreatment temperature. As a result, the deterioration of properties ofthe MISFET can be prevented.

[0127] Also, in the case where the silicon oxide film is polished by theuse of chemical solution like in the CMP method, if the silicon oxidefilm containing impurities is polished directly, the heat treatment forremoving the moisture and the like must be performed at a highertemperature and for a longer time due to its high hygroscopicity.Consequently, the heat load is further increased.

[0128] However, in this embodiment, after the silicon oxide film 61 a isdeposited to cover the bumps of the MISFETs (Qn and Qp), the siliconoxide film 61 a is planarized. Thereafter, the silicon oxide film 61 bcontaining impurities is formed. By so doing, it becomes possible toavoid the problem as described above.

[0129] In addition, since the interlayer insulating film is constitutedof the silicon oxide films 61 a and 61 b, the membrane stress can bereduced as described in the second embodiment. Therefore, the peelingand breaking of the wiring (including gate electrode) can also bereduced.

[0130] In the foregoing, the invention made by the inventors thereof hasbeen concretely described based on the embodiments. However, the presentinvention is not limited to the embodiments. It goes without saying thatvarious changes and modifications can be made within the scope of thepresent invention.

[0131] Particularly, the high-density plasma CVD is employed in thefirst to fourth embodiments. However, it is also possible to perform theforegoing processes by using the plasma CVD and the thermal CVDtogether.

[0132] The advantages achieved by the typical ones of the inventionsdisclosed in this application will be briefly described as follows.

[0133] An insulating film is formed on a MISFET of a memory cellcomposed of the MISFET and a capacitor formed on a main surface of asemiconductor substrate by the plasma CVD method at a temperature of450° C. to 700° C., and a silicon film for constituting a lowerelectrode of the capacitor is formed on the insulating film. Therefore,it is possible to increase the surface area of the silicon film and tosufficiently obtain the capacitance. It is also possible to reduce theload due to the heat treatment for removing the moisture and impuritiesin the insulating film, and thus, the deterioration of the properties ofthe MISFET can be prevented. Especially, in the case where the MISFETsof dual gate structure are formed around the memory cell, the propertiesof the MISFETs can be improved.

[0134] Also, a MISFET is formed on a main surface of a semiconductorsubstrate and an insulating film containing impurities is formed on theMISFET by plasma the CVD method at a temperature of 450° C. to 750° C.Therefore, the load due to the heat treatment for removing the moistureand the by-product in the insulating film can be reduced, and thus, thedeterioration of the MISFET can be prevented.

1-19. (cancelled)
 20. A semiconductor integrated circuit device,comprising: (a) a MISFET formed on a main surface of a semiconductorsubstrate and (b) a capacitor connected in series with said MISFET,wherein said capacitor comprises: (b1) a lower electrode made of asilicon film, which is formed at a concave portion in a lamination layerof a first insulating film formed above said MISFET and a secondinsulating film formed on said first insulating film and having smallerimpurity content than said first insulating film; (b2) a capacitorinsulating film formed on said lower electrode; and (b3) an upperelectrode formed of a conductive film formed on said capacitorinsulating film.
 21. The semiconductor integrated circuit device,according to claim 20, wherein said capacitor is connected with saidMISFET by a series of plugs which are comprised of a first plugcontacting said semiconductor substrate and a second plug contactingsaid capacitor, wherein said first plug has smaller diameter than saidsecond plug.
 22. The semiconductor integrated circuit device, accordingto claim 20, wherein a bit line is connected with said MISFET via plugswhich are comprised of a first plug contacting said semiconductorsubstrate and a second plug contacting said bit line, wherein said firstplug has larger diameter than said second plug.
 23. The semiconductorintegrated circuit device, according to claim 20, wherein a plug formedin a peripheral circuit is connected with said semiconductor substratevia a silicide layer formed on said semiconductor substrate.
 24. Thesemiconductor integrated circuit device, according to claim 20, whereinan upper surface of said lower electrode is below an upper surface ofsaid second insulating film.
 25. A semiconductor integrated circuitdevice, comprising: (a) a MISFET formed on a main surface of asemiconductor substrate; and (b) a capacitor connected in series withsaid MISFET, wherein said capacitor comprises: (b1) a lower electrodemade of a silicon film, which is formed at a concave portion in alamination layer of a first insulating film formed above said MISFET anda second insulating film which is thinner than said first insulatingfilm and formed on said first insulating film; (b2) a capacitorinsulating film formed on said lower electrode; and (b3) an upperelectrode formed of a conductive film formed on said capacitorinsulating film.
 26. The semiconductor integrated circuit device,according to claim 25, wherein said second insulating film has a smallerimpurity content than said first insulating film.
 27. The semiconductorintegrated circuit device, according to claim 25, wherein said capacitoris connected with said MISFET by a series of plugs which are comprisedof a first plug contacting said semiconductor substrate and a secondplug contacting said capacitor, wherein said first plug has smallerdiameter than said second plug.
 28. The semiconductor integrated circuitdevice, according to claim 25, wherein a bit line is connected with saidMISFET via plugs which are comprised of a first plug contacting saidsemiconductor substrate and a second plug contacting said bit line,wherein said first plug has larger diameter than said second plug. 29.The semiconductor integrated circuit device, according to claim 25,wherein a plug formed in a peripheral circuit is connected with saidsemiconductor substrate via a silicide layer formed on saidsemiconductor substrate.
 30. The semiconductor integrated circuitdevice, according to claim 25, wherein an upper surface of said lowerelectrode is below an upper surface of said second insulating film.